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RSA2-AHB Accelerator Core with AHB Interface
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General Description |
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Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. |
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The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, however, typically requiring many seconds of the CPU time for signature verification. |
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RSA2-AHB implements by far the most time-consuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices. |
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RSA2-AHB targets compact embedded designs with an ARM AHB bus. Higher performance is available from the RSA5 scalable family of cores. |
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Key Features |
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Small size: RSA1-E starts from less than 15K ASIC gates size depends on the core configuration) |
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Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications |
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Support for RSA with programmable bit sizes |
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ARM TrustZone support (separated access for normal and secure applications) |
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Test bench provided |
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Applications |
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Secure communications systems |
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Digital Rights Management (DRM) for battery powered electronics |
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Digital Signature using Reversible Public Key (rDSA) standard ANSI X9.31 |
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Digital Signature Standard (DSS) FIPS-186 |
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PKCS RSA cryptography per RFC 2347 |
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Pin Description |
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| reset |
Input |
HIGH level asynchronously resets the core. Intended to be used for simulations and testing. |
| INT |
Output |
HIGH level indicates the core has completed the operation |
| memDin[] |
Input |
Dedicated external memory input data (two ports for dual-port memory) |
| memdout[] |
Output |
Dedicated external memory output data (two ports for dual-port memory) |
| memA[] |
Output |
Address for the dedicated external memory (two ports for dual-port memory) |
| oe |
Output |
Output enable request for the dedicated external memory (two pins for dual port memory) |
| we |
Output |
Write enable for the dedicated external memory (two pins for dual-port memory) |
| AHB |
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Standard AHB signals. AXI4, APB rev. 3, and simple microprocessor interface options are available. |
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Function Description |
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| The core implements the exponentiation operation of the RSA cryptography Q = Pk. The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started. Once the operation is complete, the result Q can be read through the AHB interface.
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