SHA1, SHA2
Cryptographic Hash Cores
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General
Description |
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The SHA
cores provide implementation of
cryptographic hashes SHA-1 (core
SHA1), SHA-2 (cores SHA2-256 and
SHA2-512). |
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The cores utilize “flow-through”
design that can be easily
included into the data path of a
communication system or
connected to a microprocessor:
the core reads the data via the
D input and outputs the hash
result via its Q output. Data
bus widths for both D and Q are
parameterized. |
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The design is fully synchronous
and is available in both source
and netlist form. |
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Symbol |
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Key
Features |
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Completely self-contained; does not require external memory |
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SHA1 supports SHA-1 per FIPS 180-1, SHA2-256 and SHA2-512 support SHA-2 per FIPS 180-2. |
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HMAC option is available with flow-through and microprocessor-friendly (-SK) interfaces for the key input. |
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Flow-through design; flexible data bus width |
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Test bench provided |
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Applications |
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Message digest
calculation |
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Digital signature
(DSA) algorithm of the
Digital Signature
Standard (DSS) per
FIPS-186 |
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Security protocols, including
TLS (RFC 2246, RFC 4346)
SSL v3
PGP (RFC 2440)
SSH (RFC 4251)
S/MIME (PKCS #7, RFC 3852)
IPSec (RFC 2404, RFC 4301) |
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Pin
Description |
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CLK |
Input |
Core clock signal |
CEN |
Input |
Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored. |
START |
Input |
HIGH starting input data processing |
READ |
Output |
Read request for the input data word |
RESET |
Input |
Asynchronous reset (for simulation) |
LAST |
Input |
Last word of data signal (triggers hash output after processing) |
WRITE |
Output |
Write to the output interface |
KEYWR |
Input |
Key write signal (for HMAC -SK option) |
MODE |
Input |
Selection between hash and HMAC operations (for HMAC option) |
D[] |
Input |
Input Data Word (8/16/32 bits wide, 64 bit option for SHA2-512) |
Q[] |
Output |
Output Hash Data Word (8/16/32 bits wide, 64 bit option for SHA2-512) |
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Function
Description |
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The SHA algorithms
process data in 512-bit blocks
(SHA1, SHA2-256) or 1024-bit blocks
(SHA2-512) and produce message
digests consisting of 160 (SHA1),
256 (SHA2-256), and 512 bits
(SHA2-512).
The Secure Hash
Standard (SHA) is a message digest
standard as defined in the
FIPS-180-2 publication
http://csrc.nist.gov/publications/fips/fips180-2/fips180-2withchangenotice.pdf
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The core is designed
for flow-through operation, with
flexible-width input and output
interfaces.
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Export Permits |
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The cores are
subject to the US export regulations.
See the IP Cores, Inc. licensing basics
page,
http://ipcores.com/exportinformation.htm,
for links to US government sites and
licensing details. |
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Deliverables |
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HDL Source Licenses
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Synthesizable Verilog
RTL source code |
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Test bench
(self-checking) |
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vectors for testbenches |
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Expected results |
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User Documentation |
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Netlist Licenses
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Post-synthesis EDIF |
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Testbench
(self-checking) |
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vectors for testbenches |
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Expected results |
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Contact
Information/td>
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