| Name |
Type |
Description |
| CLK |
Input |
Core clock signal |
| RESET |
Input |
Core reset signal |
| CEN |
Input |
Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored. |
| encrypt |
Input |
When HIGH, core is encrypting, when LOW core is decrypting |
| cmac |
Input |
When HIGH, core is is performing the CMAC operation, encrypt is ignored |
| key256 |
Input |
When HIGH, 256 bit AES key is used |
| key192 |
Input |
When HIGH, 192 bit AES key is used. Cannot be asserted simultaneously with key256 |
| START |
Input |
HIGH level starts the input data processing |
| READ |
Output |
Read request for the input data byte |
| WRITE |
Output |
Write signal for the output interface |
| D[127:0] |
Input |
Input Data (other data bus widths are also available)
associated data (A), followed by the plain or cipher text |
| K[255:0] |
Input |
AES key. K[255:128] used for 128 bit key, K[255:64] used for 192 bit key |
| N[103:0] |
Input |
Nonce |
| BF[7:0] |
Input |
B0 flag byte |
| CF[7:0] |
Input |
Counter flag byte |
| lenA[15:0] |
Input |
Length of associated data in bytes (should be a multiple of 16) |
| lenC[15:0] |
Input |
Length of plain or cipher text in bytes (“payload length”) |
| Q[127:0] |
Output |
Output plain or cipher text |
| T[127:0] |
Output |
Computed MAC (tag, T) |
| DONE |
Output |
HIGH when data processing is completed |
