BCH1-1 Core, Parameterizable Compact BCH Codec
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General
Description |
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Targets the lower-performance error correction applications using Bose–Chaudhuri–Hocquenghem codes
(BCH codes) that prioritize small size over performance. |
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The performance of the BCH1-1 core is approximately 1 bit of
the codeword per clock (that is, the m = 9, n=511 word will be handled in slightly more than 511 clocks).
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Key
Features |
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Highly paramterizable |
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Very low area(in the largest,n = 511 t = 16 configuration, the core uses just 17K gates in ASIC) |
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Entirely self-contained (no external RAM required) |
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Function
Description |
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The design is configurable in terms of data size and maximum number of corrected errors. The core, during
instantiation, can support one of the Bose-Chaudhuri-Hocquenghem codes BCH(n,k,t).
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m (the exponent in the formula n = 2m-1 for the total number of bits in the codeword) varies between 4 and
9
2
(n is between 15 and 511) |
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t (the maximum number of errors that can be corrected) varies between 2 and 16 |
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For each pair of m and t, the maximum value of k (number of data bits) is determined by (n, t). The
“shortened” codes with value of k smaller than the maximum are supported
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The optimal generation polynomial is selected automatically
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Pin Description
| Name |
Type |
Description |
| clk |
Input |
Core Clock Signal |
| cen |
Input |
Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored. |
| rst |
Input |
Synchronous enable signal. When LOW the core is placed into reset. |
| D |
Input |
Input Data. For encoder input, the data to be protected by the BCH code. For
decoder input, the data to be protected followed by the “error correction” (“parity”)
bits. |
| Q |
Output |
Output Data. For decoder output, the data to be protected by the BCH code. For
encoder output, the data to be protected followed by the “error correction” (“parity”)
bits. |
| Dvalid |
Input |
HIGH indicated to the core that the valid data is available on the D bus |
| Qvalid |
Output |
HIGH indicated to the external circuitry that the valid data is available on the Q bus |
| Dready |
Output |
HIGH indicates to the external circuitry that the core is ready for data on the D bus |
| Qready |
Input |
HIGH indicated to the core that the external circuitry can accept the data on the Q
bus |
| Dstart |
Input |
A HIGH pulse indicates the start of the input data word (for the -E core) or codeword
(for the -D core) |
| Qstart |
Output |
A HIGH pulse indicates the start of the output data word (for the -D core) or codeword
(for the -E core) |
| strobe |
Output |
A HIGH level indicates the validity of the error flags |
| Cecnt |
Output |
A number if corrected errors. |
| NCerr |
Output |
A non-correctable error flag. HIGH level indicates that non-correctable errors were
found, the decoded data shall be ignored. |
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Export Permits |
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| US Bureau of Industry and Security has assigned the export control classification number 5E002 to the core. See the IP Cores, Inc. licensing basics page, http://ipcores.com/exportinformation.htm, for links to US government sites and more details. |
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Deliverables |
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HDL Source Licenses
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Synthesizable Verilog
RTL source code |
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Test bench
(self-checking) |
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Test vectors |
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Expected results |
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Software Development Kit (SDK)
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User Documentation
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Contact
Information |
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