The CEC1-66/2112 core implements the codec
for the Forward Error Correction (FEC) cyclic code (2112,2080)
used in the IEEE 802.3ap (10G Backplane Ethernet) standard and
IEEE 802.3ba (40 Gbps/100 Gbps operation). The encoder and
decoder functions are completely independent and packaged as
two sub-cores, CEC1-66/2112E and CEC1-66/2112D respectively.
Decoder corrects a single burst error of upto 11 bits.
Key Features
Small Size
Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
10G/40G/100G Ethernet MAC-friendly interface
Practically self-contained: requires only memory for one 2112-bit block in the decoder.
Flow-through design; low latency
Symbol
Applications
10/40/100G Ethernet MAC
Pin
Description
Name
Type
Description
CLK
Input
Core clock signal
EN
Input
Synchronous enable signal.
When LOW the core ignores all
its inputs and all its outputs
must be ignored.
reset
Input
Asynchronous reset
D[65:0]
Input
Input data
Q[65:0]
Output
Output data
mD[64:0]
Output
Output data to Memory
mQ[64:0]
Input
Input data to Memory
mAR[4:0]
Output
Memory Read Address
mAW[4:0]
Output
Memory Write Address
mCE
Output
Memory Clock Enable (duplicates the cen input)
locked
Output
Core has locked to the input data
strobe
Output
Cerr and NCerr outputs are valid
Cerr
Output
Error has been corrected
Ncerr
Output
Uncorrectable errors detected
Function
Description
The CEC1-66/2112E core
implements the FEC encoder per section
74 of the IEEE 802.3 standard.
