Palo Alto, California, January 10th, 2023 –IP Cores, Inc. has announced a new member of SHA3 family of cryptographic hash IP cores

The SHA3 core family implements the Keccak-based algorithms. The architecture of the family is scalable and supports fine granularity for the size/performance tradeoffs. In addition to the requirements of the FIPS 202 and NIST SP 800-185 standards, an HMAC option per FIPS 198-1 is also available. 

Palo Alto, California, June 4th, 2018 – IP Cores, Inc.  has announced modifications of its MSP10-512 cores that support line-speed MACsec encryption and decryption for the 400 Gbps Ethernet.

“Our successful MSP10 MACsec core family has been upgraded to reduce the footprint in the ASICs utilizing advanced semiconductor nodes,” said Dmitri Varsanofiev, CTO of IP Cores, Inc.  “The core is fully integrated with secure association context lookup and MACsec header parsing, validation, insertion, and removal.”

MSP10 400 Gbps Ethernet Encryption Core

MSP10 MACsec IP core delivers full 400 Gbps data rate on any frame mix, including the shortest 64-byte Ethernet frames. Variety of the core configurations permits up to tens of thousands of concurrently active secure associations. All popular features of the upcoming revision of the IEEE 801.1AE MACsec standard are supported, including the 64-bit extended packet numbering (a.k.a. IEEE 802.1AEbw, XPN) and GCM-AES-256 encryption (a.k.a. IEEE 801.1AEbn). MSP10 IP cores support channelization (a.k.a. fracturability, ability to process in time-multiplexed fashion, for example 1x400 Gbps stream, 2x200 Gbps, 1x200 + 1x100 + 2x50 Gbps, etc.).

Palo Alto, California, May 29th, 2018 – IP Cores, Inc.  has announced additional shipments of the cores from its RS200 forward error correction IP core family that supports the IEEE 50, 200, and 400 Gbps standards.

“RS200 is a well-known series of cores that follow in the footsteps of our hugely successful RS100 family,” said Dmitri Varsanofiev, CTO of IP Cores, Inc.  “Our developers will keep tracking the progress of the fast-moving IEEE 802.3 standardization group, so that our customers always have access to the FEC IP cores that are reflecting the Clause 91 and Clause 134 in the latest versions of the standards”. 

IIEEE 50G, 200G, and 400G Ethernet

IEEE 802.3bs (http://www.ieee802.org/3/bs/) standardization group had added 400 Gbps data rate to PHYs to the IEEE 802.3 Ethernet specification and and IEEE 802.3cd (http://www.ieee802.org/3/cd/) is adding the 50, 100, 200 Gbps. RS200 cores, shipping for more than a year, support the ASIC designs targeting these standards and are available in a variety of bus widths and target clock rates.

Palo Alto, California, May 23rd, 2018 – IP Cores, Inc.  has announced shipment of a 32-bit core from its popular low-power FFT core family, FFT1.

“Our popular low-power FFT1 core family now includes a high-accuracy 32-bit core FFT1-32,” said Dmitri Varsanofiev, CTO of IP Cores, Inc.  “The core delivers the similar microwatts-level power consumption as the original 16-bits-and-below versions. To further reduce the power consumption the FFT1-32 is capable of running with the reduced precision if lower accuracy is required by an application”

Palo Alto, California, Sep 25th, 2012 – IP Cores, Inc., California, USA has announced a new forward error correction core that supports the future IEEE 100 Gbps standard.

“New Reed-Solomon cores extend our portfolio of error-correction encoders and decoders ,” said Dmitri Varsanofiev, CTO of IP Cores, Inc.  “These products will speed up the design cycles in the heating up 100 Gbps backplane Ethernet market. Our developers will keep tracking the progress of the fast-moving IEEE 802.3bj standardization group, so that our customers always have access to the FEC IP cores that are reflecting the Clause 91 in the latest draft of the standard”. 

IEEE 802.3bj Backplane Ethernet

IEEE 802.3bj standardization group aims to add the 4-lane 100 Gbps PHY to the IEEE 802.3 Ethernet specification for operation on backplanes and twinaxial copper cables to provide a lower cost, lower power, and higher density solution than the current 100GBASE-CR10 standard.

The base FEC cores support the RS(528, 514) Reed-Solomon code that us used in the 100GBASE-CR4 or 100GBASE-KR4 PHYs of the draft standard. An RS(544, 514) option for 100GBASE-KP4 PHY is also available. IP cores are available for an immediate delivery.

Palo Alto, California, Jan 3rd, 2012 – IP Cores, Inc., California, USA (http://www.ipcores.com)  has announced new Low Density Parity-check Code (LDPC) designs.

“New LDPC cores extend our portfolio of error-correction encoders and decoders ,” said Dmitri Varsanofiev, CTO of IP Cores, Inc.  “These products will help our customers to design state of the art error correction capabilities into their systems”. 

Low Density Parity-check Codes

LDPC codes are frequently used in applications where efficient information transfer or storage is needed in the presence of data-corrupting noise.  LDPC codes, also known as Gallager codes, were developed by Robert G. Gallager in 1960, but are getting very popular recently. The attractiveness of the LDPC code is helped by the absence of patent issues.

Palo Alto, California, December 27th, 2011 --IP Cores, Inc., California, USA (http://www.ipcores.com) has announced additional design wins for its flagship true random number generator IP core, TRNG1.

“Our true random generator IP cores are in high demand among ASIC and FPGA designers looking for a true random number source to use in cryptographic applications,” said Dmitri Varsanofiev, CTO of IP Cores, Inc.  “Our innovative design of the hardware true random number generator (TRNG) requires no special handling during the physical design stages”. 

True Random Number Generators

True Random Number Generators (TRNG) are critical security blocks typically utilized to generate random numbers for secret cryptographic keys as well as seeds for pseudo-random number generators. A good-quality random number generator is essential for security, since generating the keys from a poor random source will significantly reduce the entropy of the long keys and might allow a brute-force attack on the seed that generated the key. A typical embedded application usually does not have access to high-quality randomness sources, so a designer of a System-on-a-Chip (SoC) targeting such application might want to instantiate a true-random source on the chip.

Many TRNG designs rely exclusively on physical features (ring oscillators or metastability) that require awareness and caution from the back-end designer doing placement and routing. IP cores, Inc. in its TRNG1 design has avoided the potential sources of these problems thus allowing the back-end processing with little or no extra effort  spent on TRNG1. For example, a typical FPGA instantiation of the TRNG1 requires no special scripts or tool configuration whatsoever.

Palo Alto, California, January 11th, 2011 -- IP Cores, Inc., California, USA (http://www.ipcores.com) and Legend Design Technology, Inc., a California company with a branch in Taiwan (http://www.LegendDesign.com), have entered into a representation agreement. The agreement provides for Legend Design,  to handle the entire line of products of IP Cores, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), cryptographically secure pseudo-random number generators (CS PRNG), Snow 3G cipher for LTE, SHA-1, SHA-256, SH-512 secure hashes, low-latency fixed and floating-point FFT and IFFT cores, high-throughput lossless compression  and error-correction cores. All cores in the IP Cores’ portfolio are targeted for both ASICs and all popular FPGA lines.

“Our products have generated a lot of interest in Taiwan,” said Dmitri Varsanofiev, CTO of IP Cores, Inc.  “With Legend Design representing our extensive portfolio of cryptographic and DSP products, we target high performance wired and wireless communication and storage markets, as well as low power and defense/government products. All of these sectors are well developed in Taiwan ”. 

"We are excited to have IP Cores as a part of our portfolio," said Dr. You-Pang Wei, president and CEO of Legend Design Technology, Inc., " IP Cores best in class encryption, compression, error correction and DSP cores together with an extraordinary technical support and flexibility are in the right position to meet the demanding ASIC and FPGA designs in Taiwan semiconductor industry."

Palo Alto, California, November 16th, 2010  --  IP Cores, Inc. (http://www.ipcores.com) has licensed its encryption technology to Space Systems/Loral (SS/L) for satellite applications.  The IP Cores solution will be used in conjunction with SS/L’s advanced satellite control subsystem to provide extremely high security for satellite communications. 

"Our new encryption solution is standard-based, extremely compact, and resistant against the single-event upset (SEU)," said Dmitri Varsanofiev, CTO of IP Cores. "This solution is therefore well-suited to be used for satellite-based encryption".

Compact Self-Contained Core Simplifies Design-In

IP Cores, Inc. is the leading company in the area of ultra-compact implementation of the standard encryptions technology. Miniature sizes of the cores offered by IP Cores, Inc. permit an efficient implementation utilizing the existing low-power space-qualified hardware solutions.  

Resistance Against SEU Permits Mission-Critical Applications

Single event upset (SEU) is a result of the change of the circuit state caused by an ionizing particle or radiation striking an element of a micro-electronic device. Probability of such change, typically resulting in a “soft error”), is increasing with the altitude and is much more pronounced in space, where high energy ionizing particles (galactic cosmic rays), solar particles and high energy protons trapped in the Earth's magnetosphere exist as part of the natural background.

 .  

Palo Alto, California, June 29th, 2010 -- IP Cores, Inc. (http://www.ipcores.com) has shipped first member of its new high-speed lossless data compression / encryption IP core family.  
 
"Our new LXP2 family of IP cores supports lossless data compression with practically unlimited block size as well as AES-XTS encryption standardized by NIST," said Dmitri Varsanofiev, CTO of IP Cores. "Tight coupling between compression and encryption enables simple integration and low latency; both features beneficial for any high-speed storage application, including enterprise solid-state (flash) drives". 
 
AES-XTS Encryption

XTS is a short name for “XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing (CTS)”. Ciphertext stealing provides support for sectors that are not multiples of  AES data block size, for example, 520-byte sectors common in the flash storage.

XTS-AES was originally standardized by the IEEE P1619 group. In January of 2010, NIST supported the XTS mode by issuing the Special Publication (SP) 800-38E^; a recommendation for the XTS-AES mode of operation, as standardized by IEEE Std 1619-2007. Per SP 800-38E, "In the absence of authentication or access control, XTS-AES provides more protection than the other approved confidentiality-only modes against unauthorized manipulation of the encrypted data."

Lossless Compression 

Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data.  Lossless compression is used when it is important that the original and the decompressed data be identical, or when no assumption can be made on whether certain deviation is uncritical. Typical applications include data storage and transmission. 

LXP2 Family of Cores 

LXP2 implements the lossless compression and encryption algorithms on units of data (“blocks”). The core supports configurable maximum block sizes up to 16 megabytes (the limit imposed by the SP800-38E). The design is fully synchronous and available in multiple configurations varying in bus widths and throughput. 

LZR1 can easily deliver few Gbps of throughput in both FPGA and ASIC implementations. The compression ratio greatly depends on the data and somewhat depends on the frames size; on typical file corpuses varies between 1.5 and 2. 

LXP2 datasheet is available on the IP Cores, Inc. Web site at http://ipcores.com/lxp2_ compression_encryption_ip_core.htm .  

For more information about IP Cores’ product line, please visit www.ipcores.com .

 Palo Alto, California, June 22nd, 2010 -- IP Cores, Inc. (http://www.ipcores.com) has shipped another version of its high-speed lossless data compression IP core.  
 
"Our new core in the LZR1 family of cores supports lossless data compression with large block size ," said Dmitri Varsanofiev, CTO of IP Cores. "As all other cores in the LZR1 family, the core is scalable with throughputs of 10 Gbps easy to achieve in both ASIC and FPGA". 
 
Lossless Compression 

Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data.  Lossless compression is used when it is important that the original and the decompressed data be identical, or when no assumption can be made on whether certain deviation is uncritical. Typical applications include data storage and transmission. 

LZR1 Family of Cores

LZR1 implements the lossless compression algorithm on short units of data (“frames”). The core supports configurable maximum frame sizes. The design is fully synchronous and available in multiple configurations varying in bus widths and throughput. 

LZR1 can easily deliver 10 Gbps of throughput in both FPGA and ASIC implementations. The compression ratio greatly depends on the data and somewhat depends on the frames size; on typical file corpuses varies between 1.5 and 2. 

GCE1 datasheet is available on the IP Cores, Inc. Web site at http://ipcores.com/lzr1_lossless_compression_ip_core.htm  

For more information about IP Cores’ product line, please visit www.ipcores.com .  

Palo Alto, California, March 23rd, 2010 -- IP Cores, Inc. (http://www.ipcores.com) has shipped an AES encryption IP core supporting the new EAX’ encryption mode.  
 
"Our new GCE1 family of cores supports EAX’, GCM, CCM, and CCM* encryption modes of the AES (Rijndael) cipher," said Dmitri Varsanofiev, CTO of IP Cores. "These are the modes that the designers of chips for wireless or wired remote sensing are typically using. In particular, the well-known EAX mode in its new and simplified EAX’ version has been chosen as a method of encryption and authentication by the authors of the ANSI C12.22 standard for transport of meter-based data over a network.  Semiconductor manufacturers working on sensor designs can future-proof their work by using our GCE1 core that supports all the encryption modes used in the standards for remote sensing, both current and upcoming". 
 
EAX and EAX’ 

EAX mode of operation for cryptographic block ciphers implements authenticated encryption with Associated Data (AEAD) algorithm to simultaneously provide both authentication and privacy for the communication link (so called authenticated encryption) via a two-pass operation, with one pass delivering privacy and one authenticity for each message. 

The EAX mode is similar in properties to the extensively used CCM mode, but has some important advantages. EAX is "on-line", i.e., it that can process a stream of data without knowing the total data length in advance and the algorithm can pre-calculate static associated data (AD), which useful for encryption/decryption of communication session parameters (where session parameters may represent the Associated Data). 

A simplified version of the EAX mode, so called EAX' , was used by the authors of the the ANSI C12.22 standard for transport of meter-based data over a network. 

GCE1 Family of Cores

GCE1 cores implement Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard (AES) and encryption/authentication modes GCM, CCM, CCM*, and EAX’. These cores process 128-bit blocks using 128-bit keys and have microprocessor-friendly register interface. 

GCE1 datasheet is available on the IP Cores, Inc. Web site at http://ipcores.com/gcm_ccm_eax_ip_core.htm  

For more information about IP Cores’ product line, please visit www.ipcores.com .  

Palo Alto, California, March 16th, 2010 -- IP Cores, Inc. (http://www.ipcores.com) has announced first shipments of a new version of IP cores from its SHA family of cores performing cryptographic hash algorithms. Cryptographic hashes are widely used in the secure communication protocols.  
 
"We updated our SHA family of cores to support an HMAC function inside the core," said Dmitri Varsanofiev, CTO of IP Cores. "The integration of the SHA cores with traditional public-key digital signature algorithms, like RSA or ECDSA became much easier." 
 
SHA Hash Functions and HMAC 

The SHA cryptographic hash functions are designed by the National Security Agency (NSA) and published by the National Institute of Standards and Technology (NIST) as a U.S. Federal Information Processing Standard (FIPS). The name of SHA stands for a Secure Hash Algorithm. The two SHA algorithms currently used are called SHA-1 and SHA-2. The SHA-2 algorithm comes in four versions with different digest sizes usually called SHA-224, SHA-256, SHA-384, and SHA-512. 

HMAC (Hash-based Message Authentication Code) is an algorithm for calculating a message authentication code (MAC) that involves a cryptographic hash function along with a secret key. It is used to verify both the data integrity and the authenticity on a communication link. 

SHA Family of Cores 

Original SHA-224, SHA-256, SHA-384, and SHA-512 cores have implemented the corresponding versions of the SHA algorithm, leaving the HMAC implementation in the external wrapper. 

The new “stored key”  (-SK) option of these cores integrate the HMAC calculation into the core. While larger than their non-HMAC counterparts, the –SK cores are very compact. For example, a SHA-256/8-SK requires just 19K ASIC gates (the original SHA-256/8 used 11K gates).  

SHA datasheet is available on the IP Cores, Inc. Web site at http://ipcores.com/sha_ip_core.htm . 

For more information about IP Cores’ product line, please visit www.ipcores.com .

IIP Cores, Inc. Announces a New Low-Latency Family of Silicon IP Cores Supporting the GCM-AES Mode as Defined by the NIST Publication SP800-38D and Used by Wireless Communication Standards IEEE 802.11ad and WiGig. Starting at 64K ASIC Gates and Throughput of 20 Gbps for the Low-End GCM5-32 Core, GCM5 Family of Cores Provides an Efficient Encryption Solution for an SoC Designer that Has to Work with Very Short Communication Data Packets and Multi-Gigabit per Second Data Rates.

Palo Alto, CA February 2, 2010 -- IP Cores, Inc today announced shipments of a new scalable family of IP cores supporting the GCM-AES mode as defined by NIST publication SP800-38D. New GCM5 IP cores provide exceptionally low latency and thus enable efficient datapath design for System on Chip (SoC) vendors meeting the challenge of handling extremely short communication frames at multi-Gbps data rates implementing the new communication standards IEEE 802.11ad (Very High Throughput 60 GHz) and WiGig.

"Our existing families of the AES/GCM IP cores enabled multiple designers of high-speed networking equipment to encrypt and decrypt Ethernet data packets at line speeds of 10 Gbps, 40 Gbps , and 100 Gbps. With the arrival of the new wireless standards, we faced a requirement to handle data frames that are both shorter than the minimum Ethernet frame size and have a preamble shorter than that in the Ethernet standards ", said Dmitri Varsanofiev, CTO of IP Cores. "Our customers were able to meet this challenge by using the cores from our new GCM5 family that enabled them to handle these short frames at line-speed."

Low-Latency AES-GCM Encryption and Decryption

Advanced Encryption Standard (AES) is used in the current proposals in front of the Wireless Gigabit Alliance (WiGig) and the IEEE standard group 802.11ad. Addressing the market demand for high-speed AES crypto solutions for this market, IP Cores' GCM5 implements the AES/GCM mode. GCM5 is designed for throughput between 25.6 and 128 Mbits per MHz.

GCM5 configurations support AES/GCM encryption and decryption throughput up to 100+ Gbps in a single core using 65 nm process, with easy parallelization to reach throughputs well beyond that number. Gate count for a fully self-contained GCM5-32 starts at 64K gates.

GCM5 family contributes to the IP Cores' fast-growing portfolio of AES-based security IP cores. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. For more information about IP Cores' product line, please visit www.ipcores.com.

IP Cores, Inc. Announces an Update of the ECC1 Elliptic Curve Cryptography (ECC) Accelerator that Simplifies the ECDH and ECDSA firmware implementation.

Palo Alto, California, January 26th, 2010 -- IP Cores, Inc. has announced availability of a revision 2 of its popular ECC1 elliptic curve acceleration IP core. Elliptic Point Cryptography (ECC) is widely used in secure communication devices, smart cards, RFID and medical applications.  

"The goal of the update was to greatly simplify the typical software integration, while keeping the extremely low resources required by the core – at less than 10 thousand ASIC gates , ECC1 is smaller than any other ECC core on the market – and the high throughput at 5,000 point multiplications per second," said Dmitri Varsanofiev, CTO of IP Cores. "The sample software implementation for elliptic curve Diffie-Hellman algorithm (ECDH) and digital signature algorithm (ECDSA) that we ship with the core became few times smaller and essentially trivial. Our existing ECC1 customers will get the updated core and matching software free of charge."

IP Cores, Inc. enters third year of its agreement with Phoenix Technologies Ltd. to represent it in Israel.

Palo Alto, California, January 20, 2010 – IP Cores, Inc., California, USA enters the third successful year of Phoenix Technologies Ltd. acting as its representative in Israel. The 2008 agreement provided for Phoenix Technologies Ltd.  to handle the entire line of products of IP Cores, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), cryptographically secure pseudo-random number generators (CS PRNG), Snow 3G cipher for LTE, SHA-1, SHA-256, SH-512 secure hashes, low-latency fixed and floating-point FFT and IFFT cores, high-throughput lossless compression cores. All cores in the IP Cores’ portfolio are targeted for both ASICs and all popular FPGA lines.

“Our products generated a lot of interest in Israel that translated into successful sales through Phoenix Technologies,” said Dmitri Varsanofiev, CTO of IP Cores, Inc.  “With an extensive portfolio of cryptographic and DSP products, we target high performance wired and wireless communication and storage markets, as well as low power and defense/government products. All of these sectors are quite well developed in Israel ”. 

"We are excited to have IP Cores as a part of our portfolio," said Benny Munitz, Product Line Manager at Phoenix Technologies. " IP Cores best in class security and FFT cores together with an extraordinary technical support and flexibility are in the right position to meet the demanding ASIC and FPGA designs done in Israeli industry.  "

IP Cores, Inc. announces a new version of the ECC1 Elliptic Curve Cryptography (ECC) accelerator with very low gate count, high performance, and low power consumption. .

Palo Alto, California, April 15th, 2009 -- IP Cores, Inc. has announced availability of a new version of the ECC1 elliptic curve acceleration IP core. Elliptic Point Cryptography (ECC) is widely used in secure communication devices, smart cards, RFID and medical applications.  

"Our new ECC accelerator design combines extremely low resources – at less than 10 thousand ASIC gates , ECC1 is smaller than any other ECC core on the market – and high throughput at 5,000 point multiplications per second," said Dmitri Varsanofiev, CTO of IP Cores. "It is well known that the basic operation of ECC is not covered by any active patent. During the implementation, we carefully avoided all patented “optimizations” and produced a patent-free core for our customers."

Elliptic Curve Cryptography
 
Elliptic curve cryptography (ECC) is an approach to public-key cryptography based on the algebraic structure of elliptic curves over finite fields. The use of elliptic curves in cryptography was suggested independently by Neal Koblitz and Victor S. Miller in 1985. U.S. National Security Agency has endorsed ECC technology by including it in its Suite B set of recommended algorithms and allows their use for protecting information classified up to top secret with 384-bit keys.
 
ECC1 Core
 
Implementation of the ECC in hardware has few important advantages over the software-only solutions. For smaller CPUs of the battery-powered devices hardware improves both the user experience and the battery life, allowing a typical Diffie-Hellman public key exchange to be completed in few milliseconds. Due to its extremely small size (ECC1 occupies area of just 0.026 square mm in the 90 nm process) – and matching low power consumption –  hardware ECC implementation enables standard public key cryptography on smart cards and RFID devices. Furthermore, a proper hardware implementation due to its inherent high throughput can avoid the optimized implementation techniques and thus be unencumbered by the patents.    
 
IP Cores, Inc. had designed the ECC1 core that implements the necessary crypto functionality of the ECC algorithm (point multiplication and point verification functionality) and weighs in at less than 10,000 ASIC gates, 630 slices on Xilinx Virtex-5 devices, 2065 LE in Altera Cyclone II, 1137 ALUT in Altera Stratix II, and 7790 tiles for Actel ProASIC3. The throughput of ECC1 reaches 5,000 point multiplies per second. ECC1 datasheet is available on the IP Cores, Inc. Web site at www.ipcores.com/images/ECC1core.pdf .
 For more information about IP Cores’ product line, please visit www.ipcores.com .

About IP Cores, Inc.

IP Cores is a rapidly growing company in the field of security and DSP IP cores. Founded 4 years ago, the company provides IP cores for communications and  storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), cryptographically secure pseudo-random number generators (CS PRNG), lossless data compression cores as well as low-latency fixed and floating-point FFT, IFFT, and Viterbi detector cores.

IP Cores, Inc. announces version of the Snow 3G cipher for 3GPP LTE communications with very low gate count and power consumption.
 
Palo Alto, California, April 7th, 2009 -- IP Cores, Inc. has announced availability of a version of the SNOW 3G cipher core with very low gate count and power consumption. Along with the ultracompact AES cipher, this cores can be used in the new mobile communication devices for 3GPP LTE networks.  

"Innovative design decisions allowed us today to offer to our customers a SNOW 3G cryptographic core that is two times smaller than the cores currently on the market," said Dmitri Varsanofiev, CTO of IP Cores. "In the encryption field, power consumption is typically proportional to the number of gates, so our cores yield substantial power savings for battery-operated designs."

Ultracompact Encryption Cores
 
The modern mobile data communications standard, 3GPP Long Term Evolution (3G LTE), uses for encryption one of the two ciphers: Advanced Encryption Standard (AES) or SNOW 3G.
 
The SNOW 3G encryption algorithm had been evaluated by the ETSI SAGE and chosen as the stream cipher for the 3GPP interfaces UEA2 and UIA2. IP Cores, Inc. had designed the SNOW3G1 core that implements the necessary crypto functionality of the algorithm and weighs in at just 7,500 ASIC gates for the data rates and clock frequencies associated with the 3GPP Long Term Evolution (3G LTE) with the maximum throughput of 7.5 Gbps. The core is fully self-contained and requires no external memory. SNOW3G1 datasheet is available on the IP Cores, Inc. Web site at www.ipcores.com/images/Snow3G.pdf .
 
For more information about IP Cores’ product line, please visit www.ipcores.com .

About IP Cores, Inc.

IP Cores is a rapidly growing company in the field of security and DSP IP cores. Founded 4 years ago, the company provides IP cores for communications and  storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), cryptographically secure pseudo-random number generators (CS PRNG), lossless data compression cores as well as low-latency fixed and floating-point FFT, IFFT, and Viterbi detector cores.

IP Cores, Inc. announces a version of the 3GPP Kasumi cipher with very low gate count and low power consumption.
 
Palo Alto, California, April 2nd, 2009 -- IP Cores, Inc. has announced availability of a version of the Kasumi cipher with very low gate count and power consumption. Along with the ultracompact AES cipher, this core can be used in the new mobile communication devices for 3G networks.  

"Innovative design decisions allowed us today to offer to our customers a Kasumi cryptographic core that is about two times smaller than the cores currently on the market," said Dmitri Varsanofiev, CTO of IP Cores. "In the encryption field, power consumption is typically proportional to the number of gates, so this core produces substantial power savings in battery-operated designs."

Ultracompact Encryption Core
 
The modern mobile data communications standardized through 3GPP typically use for encryption one of the three ciphers: Advanced Encryption Standard (AES), Snow 3G, or Kasumi.
 
Kasumi block cipher (also known as A5/3) had been designed by SAGE and is used in the f8 and f9 algorithms of the 3GPP data interface. The KSM1 core by IP Cores, Inc. implements the Kasumi encryption algorithm and utilizes only 5.5K gates in a typical 65 nm ASIC process. KSM1 datasheet is available on the IP Cores, Inc. Web site at www.ipcores.com/images/Kasumi.pdf .
 For more information about IP Cores, Inc.’ product line, please visit www.ipcores.com .

IP Cores, Inc. announces shipment of an encryption core to Philips Electronics Nederland BV.
 
Palo Alto, California, December 23, 2008 -- IP Cores, Inc. had demonstrated the technical superiority of its AES encryption code design by licensing its AES core to be incorporated into Philips security offerings.

"A unique combination of an extremely compact and high performance AES encryption core and attractive licensing terms has always been our main differentiation from competition," said Dmitri Varsanofiev, CTO of IP Cores. "We are very happy to add Philips to our growing list of Fortune 500 customers."

Ultracompact Encryption Core
The first IP core designed by IP Cores, Inc. in 2004 was an ultracompact AES core AES1. At just 3,000 ASIC gates, it still is the smallest self-contained AES encryption core on the market. Flexible options of the core include scalable throughput and AES key size, support for NIST encryption modes, variety of supported external interfaces, as well as resistance to simple and differential power attacks through additive data masking and operation hiding.
 
The core is FIPS-197 validated as a part of the AESAVS program by a NIST accredited laboratory, and had seen many design wins in ASIC technologies ranging from 45 to 350 nm as well as Xilinx, Altera, and Actel FPGAs.

For more information about IP Cores’ product line, please visit www.ipcores.com.

Philips is a registered trademark of Koninklijke Philips Electronics N.V. Xilinx, Altera, and Actel are respective trademarks of Xilinx, Inc., Altera Corporation, and Actel Corporation.

IP Cores, Inc. announces shipment of silicon IP cores supporting the security standards FIPS-197, IEEE 802.1AE and P1619.1 for Actel FPGA devices. Starting at 800 tiles for AES1-8E and delivering 11.2 Mbps on RTSX radiation-tolerant devices, AES and AES/GCM cores provide a compact and high-performance solution for an FPGA designer working on a secure communication solution.

Palo Alto, California, June 17, 2008 -- IP Cores, Inc., setting the new benchmark for security IP cores, had shipped AES and AES/GCM IP cores supporting the FIPS-197, IEEE 802.1AE and P1619.1 standards. AES1 and GCM1 IP cores enable FPGA vendors to add encryption to their designs utilizing less than 15% of the RT54SX72S device.

"AES1-8 and GCM1-8 cores are ideally suited for security implementations that fit into compact low-power, rad-hard and rad-tolerant devices," said Dmitri Varsanofiev, CTO of IP Cores. "Our cores enable customers to implement encryption designs with data rates in the range of 10 Mbps to more than 400 Mbps utilizing just a small fraction of a typical Actel FPGA."

AES and AES/GCM Encryption Supports Secure Communications
Advanced Encryption Standard in Galois/Counter Mode (GCM-AES) is used the IEEE standards 802.1AE for layer 2 transport security and P1619.1 for tape encryption. Addressing the market demand for ultra-compact AES crypto solutions for Actel FPAG market, IP Cores had shipped its AES1 and GCM1 cores targeted for RTSX, ProASIC, ProASIC3, IGLOO, and ProASIC Plus APA FPGA families.

AES1 and GCM1 configurations support AES and AES/GCM encryption and decryption respectively with throughputs exceeding 100 Mbps in a single core. IP Cores’ expanding portfolio of security and DSP IP cores includes AES and AES/GCM cores available in multiple configurations to meet specific throughput, power, and FPGA resource utilization targets. For more information about IP Cores’ product line, please visit www.ipcores.com. Descriptions of the GCM-AES cores are available at http://ipcores.com/MACsec-802.1AE-AES-GCM-Core.htm.

IP Cores, Inc. has shipped a silicon IP core supporting storage and networking security standards. Starting at 70K ASIC gates and delivering over 10 Gbps throughput, GXC3 cores provides a compact and efficient solution for an SoC designer working on a secure IEEE P1619 storage and IEEE 802.1AE networking solutions.

Palo Alto, California, November 5, 2007 -- IP Cores, Inc. today announced shipment of a new silicon IP core supporting the IEEE P1619 storage encryption standard, IEEE 802.1AE MACsec network data encryption standard, and legacy storage AES/CBC encryption. The new GXC3 core enables System on Chip (SoC) vendors to build compact cryptographic processors that support the AES/XTS, AES/GCM, and AES/CBC cryptographic algorithms.

"A modification of our popular GXM3 core, the GXC3 core adds support for the legacy AES/CBC encryption and decryption mode without any insignificant increase in size. With the shipment of the GXC3 combo core we enabled our customers to add the support for legacy encryption to their secure storage designs," said Dmitri Varsanofiev, CTO of IP Cores, Inc. "Our lead customers had converted their early access to GXC3 into a competitive advantage for their networked storage solutions."

High-speed Encryption Protects Data in Storage and inside the Network
Advanced Encryption Standard (AES) is widely used to provide data security in storage, both “at rest” on a hard drive or tape and on the network. Addressing the market demand for integrated high-speed AES crypto solutions for these two markets, IP Cores’ GXC3 supports the XTS-AES, GCM-AES, and CBC-AES modes in a single core. GXC3 supports 128-bit and 256-bit AES keys for design flexibility and is designed for throughput of 18.2 Mbits per MHz for a maximum throughput of 10 Gbps at 550 MHz clock frequency.

XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing (CTS) - abbreviated as XTS - mode of AES is a highly parallelizable mode used in the IEEE standard P1619 for narrow-block hard disk encryption. GXC3 also includes the Galois/Counter Mode (GCM) cipher designed to provide data security and authentication, and a support for the legacy tape and disk encryption Cipher Block Chaining (CBC) mode. AES in GCM mode allows parallel authentication implementations and therefore can be used for communication channels that require very high-speed authenticated encryption, such as supporting IEEE 802.1AE MACsec security for Ethernet networks, or IPsec RFC 4106. GXC3 configurations support AES/GCM, AES/CBC and AES/XTS encryption and decryption throughput over 10 Gbps in a single core, with easy parallelization for higher throughputs. Gate count for a fully self-contained GXC3 starts at 70K gates.

GXC3 contributes to the IP Cores’ efficient portfolio of AES-based security IP cores that includes support for AES and DES ECB, CTR, OFB, CFB modes, GCM-AES, XTS-AES, LRW-AES, and a set of AES-CCM implementations for a variety of telecommunications security standards (IEEE 802.11i Wi-Fi, 802.16e WiMAX, 802.15.3 UWB WiMedia, and 802.15.4 Zigbee). For networking and storage applications requiring much higher throughputs (40 Gbps, 100 Gbps and above), IP Cores, Inc. offers dedicated GCM and XTS core families. IP Cores, Inc. has also shipped a family of FFT DSP cores. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. For more information about IP Cores’ product line, please visit www.ipcores.com.

IP Cores, Inc. announces three low-latency Fast Fourier Transform IP cores for SoC applications in the OFDM-based communications (WiMAX, MBOA, IEEE 802.11) and GPS fields. FFT64 core and two versions of FFT1024 are very compact and provide parameterized bit width with throughput of 1 sample per clock.

Palo Alto, California, June 19, 2007 -- IP Cores, Inc., expanding its portfolio beyond security IP cores, today announced three compact FFT IP cores to support OFDM-based communication standards like WiMAX, MBOA, IEEE 802.11. New FFT1024-4, FFT1024-8, and FFT64 IP cores enable System on Chip (SoC) vendors to design extremely compact OFDM modems.

"Addition of the FFT cores to our portfolio permits us to broaden our customer base," said Dmitri Varsanofiev, CTO of IP Cores. "The FFT cores offered by IP Cores, Inc. are extremely efficient and flexible. Their compact sizes are especially useful in WiMAX MIMO applications."

OFDM-Based Communication Standards

Practically every modern communication standard – from IEEE 802.11 wireless networks to satellite communications - relies on the orthogonal frequency division multiplexing (OFDM) technology. Transmission and reception of data using the OFDM modulation requires an implementation of the Fast Fourier Transform (FFT) and inverse FFT (IFFT) in the modem.

FFT1024 configurations support either a 1024 point complex FFT, IFFT or two 512 point simultaneous transforms, which is a useful feature for supporting the IEEE 802.16e (WiMAX) standard. Gate count for a fully self-contained 10-bit FFT1024-4 starts at 50K gates (the core also uses 40 Kbits of memory). FFT1024 is capable of processing one sample per clock at frequencies up to 250 MHz in the 90 nm ASIC process and 80 MHz in an FPGA. The latency of the FFT1024-8 is 420 clocks, while the smaller FFT1024-4 has a latency of 1260 clocks.

FFT64 core delivers the 64 point complex FFT used in IEEE 802.11 standard and GPS applications.

Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. For more information about IP Cores’ product line, please visit www.ipcores.com.

IP Cores, Inc. announces an FPGA implementation of the AES Galois/Counter Mode (GCM) supporting the IEEE 802.1ae standard with real-life throughput exceeding 10 Gbps for all Ethernet frame sizes.

Palo Alto, California, June 12, 2007 -- IP Cores, Inc. demonstrated the high throughput of its AES-GCM solutions by delivering an FPGA implementation of its GCM3 core that provides true 10 Gbps throughput for 10G Ethernet equipment for all Ethernet frame sizes.

"Delivery of a true 10 Gbps GCM3 core demonstrates our commitment to the high-speed FPGA implementations," said Dmitri Varsanofiev, CTO of IP Cores. "High-speed Ethernet equipment can now easily implement the line-speed IEEE 802.1ae encryption in an FPGA."

Line-speed Ethernet Encryption Standard Support
The IEEE 802.1ae encryption standard uses the Advanced Encryption Standard (AES) in the Galois/counter mode (GCM). For most Ethernet application, maintaining the line-speed throughput for all frame sizes is essential.

IP Cores, Inc. has designed the GCM2 and GCM3 families of the AES-GCM cores to maintain full-speed throughput for all Ethernet frame sizes. This allowed the cores to reliably deliver a line-speed 10 Gbps throughput using a Xilinx Vrtex-4 FPGA even for the shortest Ethernet frames. The ASIC implementations of the same cores deliver throughputs of 70 Gbps and beyond

GCM2 family of cores core is optimized to handle 128-bit keys, while GCM3 supports 128, 192, and 256 bit AES keys. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. Gate count for a fully self-contained GCM2 or GCM3 core starts at 30K ASIC gates. For more information about IP Cores’ product line, please visit www.ipcores.com.