GCE1 AES-GCM/CCM/CCM*/EAX’ Core
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General
Description |
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The GCE1-MP core implements
Rijndael encoding and decoding in
compliance with the NIST Advanced
Encryption Standard and
encryption/authentication modes GCM,
CCM, CCM*, and EAX’. It processes
128-bit blocks using 128-bit keys. |
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GCE1-MP core is a configuration
of the GCE1 core that includes a
128-bit internal key. The
register-based interface of the
core of the core allows its easy
integration into a
microprocessor system. |
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The design is fully synchronous
and is immediately available in
Verilog (optional VHDL). |
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Key
Features |
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Scalable throughput from 0.8
bits per clock (GCE1-8MP) to
12.8 bits per clock
(GCE1-128MP) |
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Completely self-contained:
does not require external
memory |
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Supports both encryption and
decryption |
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Includes AES key expansion
and mode processing. |
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128 bit AES key, IV,
counter, tag storage |
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SRAM-like interface design for 8-bit and 32-bit buses |
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Test bench provided |
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Applications |
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IEEE 802.3ae (MACsec) |
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Zigbee, IEEE 802.15.4 |
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ANSI C 12 22 |
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IPsec RFC 4106, RFC
4543 |
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Pin
Description |
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CLK |
Input |
Core clock signal |
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CEN |
Input |
Synchronous enable signal.
When LOW the core ignores all
its inputs and all its outputs
must be ignored. |
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RESET |
Input |
HIGH level asynchronously
resets the core |
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A[2:0] |
Input |
Address bus. Selects the
internal registers: 0 -
Command/status, 1 - Data, 2
-IV/Tag, 3- Counter,4-Key |
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READ |
Input |
Read register request |
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WRITE |
Input |
Write register request |
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A[2:0] |
Output |
HIGH level indicates a
completion of an encryption step |
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D[] |
Input |
Input Data |
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Q[ ] |
Output |
Output Data |
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Function
Description |
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The Advanced
Encryption Standard (AES) algorithm
implements the NIST data encryption
standard as defined in the FIPS-197
(http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf).
GCE1 supports five
AES encryption modes: ECB encryption
per NIST SP800-38B
(http://csrc.nist.gov/publications/nistpubs/800-38D/SP-800-38B.pdf
) GCM per NIST SP800-38D
(http://csrc.nist.gov/publications/nistpubs/800-38D/SP-800-38D.pdf
), CCM per NIST SP800-38C
(http://csrc.nist.gov/publications/nistpubs/800-38D/
SP800-38C_updated-July20_2007.pdf),
CCM* per Zigbee
specification, and EAX’ per ANSI C
12 22.
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Export Permits |
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US Bureau of
Industry and Security has assigned the
export control classification number
5E002 to the AES1 core. The core is
eligible for the license exception ENC
under section 740.17(A) and (B)(1) of
the export administration regulations.
See the IP Cores, Inc. licensing basics
page,
http://ipcores.com/exportinformation.htm,
for links to the US government sites and
more details. |
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Deliverables |
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HDL Source Licenses
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Synthesizable Verilog
RTL source code |
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Software modules for a
complete ECC
implementation
(optional) |
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Verilog testbench
(self-checking) |
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Software modules test
harness |
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Vectors for testbench
and harness |
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Expected results |
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User Documentation
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Netlist Licenses
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Post-synthesis EDIF |
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Testbench
(self-checking) |
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vectors for testbenches |
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Expected results |
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Contact
Information |
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