The core is designed for flow-through operation, with 8/16/32/64/128-bit wide input and output interfaces. AKW1 supports both encryption (wrap) and decryption (unwrap) modes.
Implementation Results
Area Utilization and Performance
Representative area/resources figures are shown below.
Core Type
Technology
Area / Resources
Max Frequency
Throughput
AKW1-8D
TTSMC 0.09 µ LV
8,000 gates
250 MHz
23 Kwraps/sec
AKW1-64D
TSMC 0.09 µ LV
14,000 gates
250 MHz
186 Kwraps/sec
AKW1-128D
TSMC 0.09 µ LV
16,000 gates
250 MHz
372 Kwraps/sec
Export Permits
US Bureau of Industry and Security has assigned the export control classification number 5E002 to the AES1 core. The core is eligible for the license exception ENC under section 740.17(A) and (B)(1) of the export administration regulations. See the IP Cores, Inc. licensing basics page,
for links to US government sites and more details.
Deliverables
HDL Source Licenses
Synthesizable Verilog RTL source code
Verilog testbench (self-checking)
Vectors for testbench
Expected results
User Documentation
Netlist Licenses
Post-synthesis EDIF
Testbench (self-checking)
Vectors for testbench
Expected results
Contact Information
IP Cores, Inc.
3731 Middlefield Rd.
Palo Alto, CA 94303, USA
Phone: +1 (650) 815-7996