RSA2-AHB Accelerator Core with AHB Interface
|
 |
General Description |
|
 |
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. |
|
The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, however, typically requiring many seconds of the CPU time for signature verification. |
|
RSA2-AHB implements by far the most time-consuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices. |
|
RSA2-AHB targets compact embedded designs with an ARM AHB bus. Higher performance is available from the RSA5 scalable family of cores. |
|
|
Symbol |
|
|
|
|
|
Key Features |
|
| |
Small size: RSA1-E starts from less than 15K ASIC gates size depends on the core configuration) |
|
Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications |
|
Support for RSA with programmable bit sizes |
|
ARM TrustZone support (separated access for normal and secure applications) |
|
Test bench provided |
|
|
Applications |
|
| |
Secure communications systems |
|
Digital Rights Management (DRM) for battery powered electronics |
|
Digital Signature using Reversible Public Key (rDSA) standard ANSI X9.31 |
|
Digital Signature Standard (DSS) FIPS-186 |
|
PKCS RSA cryptography per RFC 2347 |
|
|
|
|
|
Pin Description |
|
| reset |
Input |
HIGH level asynchronously resets the core. Intended to be used for simulations and testing. |
| INT |
Output |
HIGH level indicates the core has completed the operation |
| memDin[] |
Input |
Dedicated external memory input data (two ports for dual-port memory) |
| memdout[] |
Output |
Dedicated external memory output data (two ports for dual-port memory) |
| memA[] |
Output |
Address for the dedicated external memory (two ports for dual-port memory) |
| oe |
Output |
Output enable request for the dedicated external memory (two pins for dual port memory) |
| we |
Output |
Write enable for the dedicated external memory (two pins for dual-port memory) |
| AHB |
|
Standard AHB signals. AXI4, APB rev. 3, and simple microprocessor interface options are available. |
|
|
| |
|
Function Description |
|
| The core implements the exponentiation operation of the RSA cryptography Q = Pk. The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started. Once the operation is complete, the result Q can be read through the AHB interface.
|
|
| |
|
Options |
|
The core comes in a variety of options:
• Multiplication option (CRT) provides an interface to accelerate the Chinese Remainder Theorem in hardware. Without this option, the default exponentiation-only (E) core still permits the use of the CRT, but requires some CPU support.
• Diffie-Hellmann (-DH) option accelerates an entire Diffie-Hellmann algorithm. Without this option, the DH operations requires some CPU support
• Digital Signature (DSA) option accelerates an entire Digital Signature algorithm. Without this option, the DH operations requires some CPU support |
|
|
Export Permits |
|
| The core is subject to the US export regulations. See the IP Cores, Inc. licensing basics page, http://ipcores.com/exportinformation.htm, for links to US government sites and licensing details |
| |
|
Deliverables |
|
HDL Source Licenses
|
| |
Synthesizable Verilog RTL source code |
|
Software modules for a complete ECC implementation (optional) |
|
Verilog testbench (self-checking) |
|
Software modules test harness |
|
Vectors for testbench and harness |
|
Expected results |
|
User Documentation
|
|
|
| |
|
Contact Information |
|
| |
|
