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General
Description |
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The LZR4D core implements lossless decompression of data compressed in the LZ4 format. |
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Unlike conventional few-bytes-per-clock or token-per-clock designs, the LZR4D resolves multiple LZ4 sequences concurrently within a single decompression engine, sustaining an output rate of 256 bits (32 bytes) of decompressed data per clock cycle on a single compressed stream. At the multi-gigahertz clock rates of advanced process nodes, this corresponds to terabit-class decompression throughput in a single engine, with no need to split data into independently compressed blocks across an array of slower decompressors |
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The core's decompression latency is below 30 clock cycles, which translates to an end-to-end decompression delay of 10 to 20 nanoseconds in advanced semiconductor nodes. This ultralow, deterministic latency allows the LZR4D to be placed directly in latency-critical data paths, such as compressed memory tiers, CXL-attached memory expanders, solid-state storage controllers, enterprise storage appliances, and in-network data processing, where the decompression step was previously a bottleneck. |
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Symbol |
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Key
Features |
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Single-engine architecture sustains 256 bits (32 bytes) of decompressed output per clock cycle |
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Terabit-class decompression throughput at multi-gigahertz clock frequencies |
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Ultralow, deterministic latency of under 30 clock cycles (10 to 20 ns in advanced semiconductor nodes) |
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Resolves multiple LZ4 sequences concurrently within a single decompression engine |
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No block-level stream splitting or arrays of parallel engines required |
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Suitable for placement directly in latency-critical data paths |
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Applications |
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Compressed memory tiers |
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CXL-attached memory expanders |
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Solid-state storage controllers |
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Enterprise storage appliances |
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In-network data processing |
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Network processors and memory subsystems |
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