PQC1- APB Post-Quantum Cryptography
Accelerator IP Core
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General
Description |
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Implements ML-KEM and ML-DSA
post-quantum cryptography
digital signature standards. The
system interface is an microprocessor slave bus (APB, AHB, AXI options are available). |
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The design is fully synchronous
and requires only minimal CPU
intervention due to internal
microprogramming sequencer.
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Symbol |
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Key
Features |
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Support for ML-KEM(FIPS-203,
Kyber) and ML-DSA
algorithms(FIPS-204,
Dilithium) with built-in NTT and SHAKE128/SHAKE256/SHA-3 engines accessible externally |
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Self-contained,
except for the single-port
external RAM banks |
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Uses 32-bit-wide APB Lite
interface |
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Supports all MS-DSA algorithms defined in FIPS-204 (from Category 2 ML-DSA-44, Category 3 ML-DSA-65, Category 5 ML-DSA-87) and all FIPS-203 ML-KEM algorithms (ML-KEM-512, ML-KEM-768, and ML-KEM- 1024). |
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An SDK is provided for software development with support for ML-DSA (key generation, signing, and signature
verification) and ML-KEM (key generation, key encapsulation, and key decapsulation). |
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High clock rate. Timing closure at 1 GHz clock in ASIC with easy, higher frequencies are possible. |
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Deliverables include Verilog
test bench and test vectors |
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Applications |
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Post-Quantum cryptgraphy |
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Function
Description |
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The core contains three accelerators:
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The number theoretic transform NTT accelerator also capable of other vector polynomial operations |
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The FIPS-202 accelerator supporting SHA-3, SHAKE128 and SHAKE256 algorithms |
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The packing/unpacking accelerator that handles the key and signature formats defined by FIPS-203 and FIPS-204
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True random number generator (needed for key generation or randomization of signing) is not included. The true
random generator IP core TRNG1 can be used for that purpose. |
Performance
| Operation |
Category |
Performance, ops/sec |
| ML-DSA signature generation¹ |
2 |
15,000 |
| 3 |
10,000 |
| 5 |
7,000 |
| ML-DSA key generation |
2 |
30,000 |
| 3 |
20,000 |
| 5 |
12,000 |
| ML-DSA signature verification |
2 |
33,000 |
| 3 |
21,000 |
| 5 |
13,000 |
| ML-KEM key generation |
1 |
95,000 |
| 3 |
55,000 |
| 5 |
35,000 |
| ML-KEM encryption |
1 |
65,000 |
| 3 |
40,000 |
| 5 |
28,000 |
| ML-KEM decryption |
1 |
230,000 |
| 3 |
180,000 |
| 5 |
145,000 |
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Export Permits |
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| US Bureau of Industry and Security has assigned the export control classification number 5E002 to the core. See the IP Cores, Inc. licensing basics page, http://ipcores.com/exportinformation.htm, for links to US government sites and more details. |
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Deliverables |
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HDL Source Licenses
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Synthesizable Verilog
RTL source code |
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Test bench
(self-checking) |
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Test vectors |
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Expected results |
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Software Development Kit (SDK)
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User Documentation
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Contact
Information |
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