Elliptic Curve (ECC) Point Multiply Accelerator Core
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General Description |
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Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part of the “Suite B” of crypto algorithms approved by the NSA. |
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Since ECC requires fewer bits than RSA to achieve the same cipher strength, it is frequently used in embedded applications. The operations necessary for the ECC cannot be efficiently implemented on an embedded CPU, however, typically requiring hundreds of milliseconds of the CPU time for signature verification. |
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ECC1-PM implements by far the most time-consuming operation of the ECC cryptography: so called “point multiplication” to enable low-power operation of the battery-powered devices. |
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The design is fully synchronous and available in multiple configurations varying in bus widths, set of elliptic curves supported and throughput. |
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Key Features |
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Small size: ECC1-PM starts from less than 10K ASIC gates (intermediate result storage memory required; size depends on the core configuration) |
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Implements the computationally demanding parts of ECC public key cryptography for long life battery powered applications |
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Support for ECC binary fields 2163, 2233, 2283, 2409, and 2571 |
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Microprocessor-friendly interface |
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Test bench provided |
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Applications |
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Pin Description |
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| CLK |
Input |
Core clock signal |
| CEN |
Input |
Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored. |
| RESET |
Input |
HIGH level asynchronously resets the core |
| READ |
Input |
Read request for the input data byte |
| WRITE |
Input |
Write signal for the interface |
| DONE |
Output |
HIGH level indicates a completion of computation |
| D[ ] |
Input |
Input Data |
| A[ ] |
Input |
Address |
| Q[ ] |
Output |
Output Data |
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Function Description |
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| The core implements the Point Multiplication operation of the ECC cryptography Q = kP. The operands for the multiplication: k, Px, Py are programmed through the microprocessor interface. The curve parameters a/b are selected through the microprocessor interface and the calculation is started. Once the operation is complete, the result Qx, Qy can be read through the interface.
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Export Permits |
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| The core is subject to the US export regulations. See the IP Cores, Inc. licensing basics page,
for links to US government sites and more details. |
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Deliverables |
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HDL Source Licenses
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Synthesizable Verilog RTL source code |
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Software modules for a complete ECC implementation (optional) |
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Verilog testbench (self-checking) |
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Software modules test harness |
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Vectors for testbench and harness |
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Expected results |
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User Documentation
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Netlist Licenses
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Post-synthesis EDIF |
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Testbench (self-checking) |
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vectors for testbenches |
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Expected results |
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Contact Information |
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