Implementation of the new WLAN security standard 802.11i requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and message authentication. The WPA2 AES core is tuned for 802.11i applications and as such requires much smaller gate count than a full implementation. The core contains the base AES core AES1 and is available for immediate licensing.
The design is fully synchronous and available in both source and netlist form.
8,900 ASIC gates at 802.11a/g OFDM data speeds
Completely self-contained: does not require external memory
Includes encryption, decryption, key expansion and data interface
Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC,
AES0CTR per NIST SP800-38C)
Automatic generation of key context from keydata
Test bench provided
Deliverables include test benches
WiFi 802.11i CCMP (CTR+CBC AES modes)
WPA AES and WPA2
Core clock signal
Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored.
Mode. When HIGH, transmit, when LOW receive
HIGH starting input data processing
Read request for the input data byte
HIGH when valid data byte present on the input
Write to the output interface
HIGH when output interface is ready to accept data byte
The WPA2 implementation fully supports the AES algorithm for 128 bit keys in
Counter Mode (CTR) method of encryption with CBC message integrity check as
required by the CCM protocol of the 802.11i standard and
The core is designed for flow-through operation, with byte-wide input and output interfaces. CCM key and nonce material precedes the frame in the flow of data. WPA2 supports encrypt and decrypt modes
Device Utilization and Performance
Representative area/resources figures are shown below.
Area / Resources
TSMC 0.18 u
US Bureau of Industry and Security has assigned the export control classification number 5E002 to our AES core. The core is eligible for the license exception ENC under section 740.17(A) and (B)(1) of the export administration regulations. See the licensing basics page,
for links to US government sites and more details.
HDL Source Licenses
Synthesizable Verilog RTL source code
Test bench (self-checking)
vectors for testbenches
vectors for testbenches
Place & Route script
IP Cores, Inc.
3731 Middlefield Rd.
Palo Alto, CA 94303, USA
Phone: +1 (650) 815-7996