|
|
 |
Security and DSP IP Cores for ASIC and FPGA
Applications
|
|
IP Cores, Inc. specializes on IP cores for
semiconductors, primarily in the security and
cryptography area
as well as few DSP cores. Whether your
need IP cores for 802.16e, P1619, 802.1AE,
content protection
or FFT, ours are usually the smallest,
fastest, and lowest-cost choices on the market. |
|
|
 |
 |
6/29/2010
IP Cores, Inc. Announces New Family of
Compression/Encryption IP Cores |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Tiny encryption IP cores start at few thousand ASIC
gates or few hundred FPGA slices
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SHA
SHA
cores provide implementation of
cryptographic hashes SHA-1 (core SHA1), SHA-2
(cores SHA2-256 and SHA2-512). Datasheet.
|
|
|
|
Combo GCM/CCM/EAX The GCE1-MP core implements Rijndael encoding
and decoding in compliance with the NIST Advanced
Encryption Standard and encryption/authentication
modes GCM, CCM, CCM*, and EAX’. Datasheet.
|
|
|
|
top |
|
|
|
|
|
| |
Scalable high throughput IP core families deliver
encryption at 10-100 Gbps data rates
|
|
|
GCM (IEEE802.1ae)
High-speed implementation of the AES/GCM
(Galois/Counter Mode) encryption and
decryption for
IEEE 802.1AE (MACSec) standards.
GCM1 is a compact core family starting
at less than 13K ASIC gates with target
throughput from 1 to 6 Gbps (scalable to
10 Gbps).
GCM1 Datasheet.
GCM2 is a high-performance scalable
family of cores for 128-bit AES keys and
target throughput between 5 and 40 Gbps
(scalable to 70-100 Gbps).
GCM2 Datasheet.
GCM3 core family is similar to GCM2, but
supports key sizes to 256 bits.
GCM3 Datasheet. GCM10 family
delivers the ultimate performance of 120
Gbps and above. |
|
|
|
|
|
Combo XTS/GCM A combined
high-speed implementation of the
AES-XTS and
AES-GCM modes encryption and
decryption supporting IEEE P1619 and
802.1ae standards. GXM2 is a compact
core for 128-bit keys.
GXM2 Datasheet. GXM3 core is similar
to GXM2, but allows 256-bit AES keys.
GXM3Datasheet. |
|
|
|
Combo XTS/GCM/CBC
GXC3 core addresses storage and network
storage applications that in addition to
XTS and GCM require legacy CBC mode of
the AES cipher.
GXC3Datasheet. |
|
|
10 Gbps data compression core
provides lossless data compression at
throughputs above 10 Gbps. Contact us
for the datasheet. |
|
|
|
top |
|
|
|
|
|
| |
Inline encryption IP cores provide cryptography for
communication standards
|
|
|
|
|
WiFi 802.11i CCM Core Full
flow-through implementation of the CCM
(CTR+CBC, CCMP) encryption and
decryption according to the IEEE 802.11i
(WPA, WPA2) WLAN standard. The core uses
less than 9,000 gates.Datasheet. |
|
|
|
Zigbee CCM*
A version of this core is also available
for IEEE 802.15.4 standard (IEEE
802.15.4 is used by the ZigBee Alliance
as a base of its ZigBee™ specification.
Datasheet.
Datasheet. |
|
|
|
UWB MBOA CCM Core Full
flow-through implementation of the CCM
(CTR+CBC) encryption and decryption
according to the Multi-Band OFDM (MBOA)
standard.
Datasheet. |
|
|
|
top |
|
|
|
|
|
| |
IP cores for RSA and Elliptic Curve Cryptography
(ECC) acceleration
|
|
|
RSA1-E implements the RSA
exponentiation to enable low-power
operation of the battery-powered devices
Datasheet. |
|
|
|
ECC1 implements the “point
multiplication” and "point verification"
operations, and is extremely compact at
10K gates.
Datasheet. |
|
|
ECC1-PM implements the most
time-consuming operation of the ECC
cryptography, the “point multiplication”
Datasheet. |
|
|
|
top |
|
|
|
|
|
| |
IP cores for Compression and Encryption
|
|
|
LZR1 implements the lossless compression
algorithm on short units of data (“frames”). The
core supports frame sizes up to 4096 bytes. Datasheet. |
|
|
|
LXP2 implements the lossless compression
/decompression algorithm and AES-XTS
encryption /decryption on units of data (“blocks”).
Datasheet. |
|
|
|
top |
|
| |
|
|
| |
IP core for Forward Error Correction
|
|
|
FEC Codec The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code
(2112,2080) used in the IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40
Gbps/100 Gbps operation). Datasheet. |
|
|
|
|
top |
|
|
|
|
|
|
IPsec Processor Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES
cipher in the GCM mode for encryption and message authentication, as well as header parsing and formatting
operations on the transmitted and received packets. Datasheet. |
|
|
|
MACsec Processor implements the lossless compression
/decompression algorithm and AES-XTS
encryption /decryption on units of data (“blocks”).
Datasheet. |
|
|
|
top |
|
|
|
|
| |
IP cores implement FFT and Viterbi decoder
algorithms
|
|
|
|
|
64 Point FFT high-performance
cores support FTT and IFFT transforms.
Many more variants of the FFT cores
available.
Datasheet. |
|
|
|
|
|
FFT1-32-512 core implements 32, 64, 128, 256,
and 512 point FFT and IFFT in hardware that runs at the
clock frequency four times higher than the input
sampling frequency
Datasheet. |
|
|
|
top |
|
|
|
|
|
|
|
LRW High-speed implementation
of the LRW-AES (Liskov-Rivest-Wagner)
encryption and decryption.
Datasheet. |
|
|
|
|
|
802.15.3 CCM Full
flow-through implementation of the CCM
(CTR+CBC) encryption and decryption
according to the IEEE 802.15.3 standard.Datasheet. |
|
|
|
top |
|
|
|
|
|
|
|
|
|
|
