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LRW1/LRW2/LRW3
LRW-AES Cores
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General Description
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Key Features
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Implementation
of the older drafts standard
IEEE P1619 required the NIST standard AES cipher in the LRW
mode for encryption (AES-LRW). Note that the
new drafts of the P1619 call for a different mode,
XTS-AES (see our XTS cores).
The LRW1 AES core is tuned for storage applications at the data rates of 3 Gbps and higher.
The LRW2 family of cores covers a wide range of area /
throughput combinations, allowing the designer to choose
the smallest core that satisfies the desired
clock/throughput requirements. All LRW cores contain the base AES core AES1 and
are available
for immediate licensing. LRW3 family is similar to
LRW2, but supports 256-bit AES keys and no-penalty key
and IV changes.
The design is fully synchronous and available in both
source and netlist form. |
Small size: LRW1 starts at 30,000 ASIC gates at throughput of
12.8 bits per clock
Synthesized for 600+ MHz clock speeds (70+ Gbps
throughput for LRW2-128)
Completely self-contained: does not require external
memory
Supports Liskov-Rivest-Wagner encryption and decryption
(LRW-AES a.k.a. AES-LRW)
Includes LRW-AES encryption, LRW-AES decryption, key expansion and
data interface
Flow-through design
No penalty for key and IV changes (back-to-back
operation)
128+128 bit LRW keys supported. 256+128 bit key
supported by LRW3.
Easily parallelizable for higher data rates
Test bench provided
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LRW-AES Applications
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Storage encryption
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Pin Description
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Name
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Type
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Description
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CLK
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Input
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Core
clock signal |
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CEN
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Input
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Synchronous
enable signal. When LOW the core ignores all its inputs
and all its outputs must be ignored. |
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MODE
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Input
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Mode.
When HIGH, write (LRW-AES encryption), when LOW, read
(LRW-AES decryption) |
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START
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Input
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HIGH
starting input data processing |
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READ
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Output
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Read
request for the input data byte |
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DATA_VALID
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Input
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HIGH
when valid data byte present on the input |
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WRITE
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Output
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Write
to the output interface |
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OUT_READY
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Input
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HIGH
when output interface is ready to accept data byte |
| D[127:0] |
Input |
Input
Data (plain or cipher text, other data bus widths are also available)
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K1[255:0] |
Input |
AES
key (128-bit key option is also available) |
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K2[127:0] |
Input |
Tweak
key (K2) |
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IV[127:0] |
Input |
Logical position (I) |
| Q[127:0] |
Output |
Output
plain or cipher text |
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Function Description
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The Advanced Encryption Standard (AES) algorithm is a new
NIST data encryption standard as defined in the
http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
LRW implementation fully supports the AES algorithm
for 128+128 and 256+128 bit keys LRW-AES mode as required by
the P1619 IEEE draft standard.
The cores are designed for flow-through operation, with selectable
width of input and output interfaces. LRW cores
support both encryption and decryption modes.
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Implementation Results
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Area Utilization and Performance
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| Representative area/resources figures are shown
below. |
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Core |
Technology
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Area / Resources
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Max Frequency
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Throughput
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LRW1 |
TSMC 0.13 µ LV
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29,959 gates
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100 MHz
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1.28 Gbps
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LRW1 |
TSMC 0.09 µ LV
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60,165 gates
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600 MHz
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7.68 Gbps
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LRW2-25.6 |
TSMC 0.09 µ LV |
44,405 gates |
100 MHz |
2.56 Gbps |
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LRW2-64 |
TSMC 0.09 µ LV |
84,269 gates |
100 MHz |
6.4 Gbps |
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LRW2-64 |
TSMC 0.09 µ LV |
196,914 gates |
515 MHz |
33 Gbps |
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LRW2-128 |
TSMC 0.09 µ LV |
150,817 gates |
100 MHz |
12.8 Gbps |
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LRW2-128 |
TSMC 0.09 µ LV |
311,252 gates |
305 MHz |
39 Gbps |
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LRW2-128 |
TSMC 0.09 µ LV |
399,208 gates |
550 MHz |
70.4 Gbps |
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Multiple LRW cores can be easily paralleled
for throughputs of 100 Gbps and higher.
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Export Permits
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US Bureau of Industry and Security has assigned
the export control classification number 5E002 to our AES
core. The core is eligible for the license exception ENC
under section 740.17(A) and (B)(1) of the export
administration regulations. See the
licensing basics page,
for links to US government sites and more details. |
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Deliverables
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HDL Source Licenses
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Netlist Licenses
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- Synthesizable Verilog RTL source code
- Testbench (self-checking)
- LRW-AES vectors for testbenches
- Expected results
- User Documentation
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- Post-synthesis EDIF
- Testbench (self-checking)
- LRW-AES vectors for testbenches
- Expected results
- Place & Route script
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Contact Information
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