CTR10 Family of Cores
High Performance AES-256-CTR Cores |
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General Description
When a datastream need to be encrypted at high data rates, AES cores utilizing parallelizable NIST encryption modes can be used. CTR10 is a scalable family of cores that implement the Counter (CTR) mode per NIST SP800-38A at high data rates. Depending on the configuration, 128-bit and 256-bit keys are supported. Target throughputs are between 5 and 40 Gbps. For authenticated encryption modes at high data rates, see our GCM2 and GCM3 families for AES-128-GCM and AES-256-GCM implementation respectively.
Each core contains the base AES core AES1 and is available for immediate licensing. The design is fully synchronous and available in both source and netlist form. |
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Symbols
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Pin Description
| Name |
Type |
Description |
| CLK |
Input |
Core clock signal |
| CEN |
Input |
Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored. |
| encrypt |
Input |
When HIGH, core is encrypting, when LOW core is decrypting |
| key256 |
Input |
When HIGH, 256 bit AES key is used. |
| START |
Input |
HIGH level starts the input data processing |
| READ |
Output |
Read request for the input data byte |
| WRITE |
Output |
Write signal for the output interface |
| D[127:0] |
Input |
Input Data (other data bus widths are also available) |
| K[255:0] |
Input |
AES key. If the 128-bit key is used, it shall be placed into the MSB of the K bus |
| IV[127:0] |
Input |
Initial counter value |
| Q[127:0] |
Output |
Output plain or cipher text |
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Function Description
The Advanced Encryption Standard (AES) algorithm is a NIST data encryption standard as defined in the FIPS-197 standard (http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf ).
The CTR10 implementation fully supports the CTR mode of the AES algorithm for 128/256 bit keys as required by the 802.1ae IEEE standard and NIST publication SP800-38A (http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf).
The core is designed for flow-through operation, with 128-bit wide input and output interfaces. CTR10 supports both encryption and decryption modes (for CTR mode, the same operation performs the encryption and the decryption).
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Export Permits
US Bureau of Industry and Security has assigned the export control classification number 5E002 to our AES1 core. The core is eligible for the license exception ENC under section 740.17(A) and (B)(1) of the export administration regulations. See the IP Cores, Inc. licensing basics page, http://ipcores.com/exportinformation.htm, for links to US government sites and more details.
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Deliverables
- HDL Source Licenses
- Synthesizable Verilog RTL source code
- Testbench (self-checking)
- Vectors for testbenches
- Expected results
- User Documentation
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