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WPA2 802.11i CCM (CTR+CBC) AES Core for
WiFi WLAN |
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General Description
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Key Features
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Implementation of the new WLAN security standard 802.11i
requires the NIST standard AES cipher in CTR and CBC
modes (a.k.a. CCM) for encryption and message authentication.
The WPA2 AES core is tuned for 802.11i applications
and as such requires much smaller gate count than
a full implementation. The core contains the base
AES core AES1 and is available for immediate licensing.
The design is fully synchronous and available in
both source and netlist form.
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Small size:
8,900 ASIC gates at 802.11a/g OFDM data speeds
Completely self-contained: does not require external
memory
Includes encryption, decryption, key expansion and
data interface
Support for Counter Mode Encryption (CTR) operation
and CCM extensions (Counter Mode with CBC MAC)
Automatic generation of key context from keydata
Flow-through design
Test bench provided
Deliverables include test benches
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Symbol
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Applications
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WiFi 802.11i CCMP (CTR+CBC AES modes)
WPA AES and WPA2
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Pin Description
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Name
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Type
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Description
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CLK
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Input
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Core
clock signal |
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CEN
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Input
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Synchronous
enable signal. When LOW the core ignores all its inputs
and all its outputs must be ignored. |
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MODE
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Input
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Mode.
When HIGH, transmit, when LOW receive |
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START
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Input
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HIGH
starting input data processing |
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READ
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Output
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Read
request for the input data byte |
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DATA_VALID
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Input
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HIGH
when valid data byte present on the input |
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WRITE
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Output
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Write
to the output interface |
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OUT_READY
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Input
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HIGH
when output interface is ready to accept data byte |
| D[7:0] |
Input |
Input
Data |
| Q[7:0] |
Output |
Output
Data |
| DONE |
Output |
Data
processing completed |
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Function Description
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The Advanced Encryption Standard (AES) algorithm is a new
NIST data encryption standard as defined in the
http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
The WPA2 implementation fully supports the AES algorithm
for 128 bit keys in Counter Mode (CTR) method of encryption
with CBC message integrity check as required by the CCM
protocol of the 802.11i standard.
The core is designed for flow-through operation, with byte-wide
input and output interfaces. CCM key and nonce material
precedes the frame in the flow of data. WPA2 supports encrypt
and decrypt modes
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Implementation Results
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Device Utilization and Performance
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| Representative area/resources figures are shown
below. |
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Technology
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Area / Resources
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TSMC 0.18 u
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8900 gates
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Altera FPGA
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1362 LUT
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Xilinx FPGA
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866 slices
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Export Permits
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| US Bureau of Industry and Security has assigned
the export control classification number 5E002 to our AES
core. The core is eligible for the license exception ENC
under section 740.17(A) and (B)(1) of the export
administration regulations. See the
licensing basics page
for links to US government sites and more details. |
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Deliverables
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HDL Source Licenses
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Netlist Licenses
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- Synthesizable Verilog RTL source code
- Testbench (self-checking)
- Vectors for testbenches
- Expected results
- Simulation script
- Synthesis script
- User Documentation
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- Post-synthesis EDIF
- Testbench (self-checking)
- Vectors for testbenches
- Expected results
- Place & Route script
- Simulation script
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Contact Information
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