Ultracompact AES Core
 64 Point FFT Core
1024 Point FFT Core
XTS/ XEX/GCM core
XTS-AES P1619 core
GCM (802.1ae)  Core
DES/3DES Core
AES Key Wrap
802.16e WiMAX CCM Core
802.11i CCM Core
UWB MBOA CCM Core
DTCP IP Cores
Zigbee CCM* Core
802.15.3 CCM Core
LRW-AES Core
Combo LRW/GCM core
 
 
6/17/2008
AES-GCM Cores Shipped for Actel FPGA


10/5/2007 GCM/XTS/CBC core shipped

6/19/2007 Three FFT cores announced

6/12/2007 AES-GCM core reaches 10 Gbps on an FPGA

10/17/2006 AES1-32E gets a FIPS 197 validation

 

Information on
Export Licensing

 

IP Cores, Inc.
3731 Middlefield Rd.
Palo Alto, CA 94303, USA
Phone: +1 (650) 815-7996

E-mail: info@ipcores.com
www.ipcores.com
 
 
 
 
 
 

WPA2 802.11i CCM (CTR+CBC) AES Core for WiFi WLAN

 

General Description

Key Features

   

Implementation of the new WLAN security standard 802.11i requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and message authentication. The WPA2 AES core is tuned for 802.11i applications and as such requires much smaller gate count than a full implementation. The core contains the base AES core AES1 and is available for immediate licensing.

The design is fully synchronous and available in both source and netlist form.

Small size:

8,900 ASIC gates at 802.11a/g OFDM data speeds

Completely self-contained: does not require external memory

Includes encryption, decryption, key expansion and data interface

Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC)

Automatic generation of key context from keydata

Flow-through design

Test bench provided

Deliverables include test benches

   

Symbol

Applications

   
  • WiFi 802.11i CCMP (CTR+CBC AES modes)
  • WPA AES and WPA2
  •  

    Pin Description

     
    Name
    Type
    Description
    CLK
    Input
    Core clock signal
    CEN
    Input
    Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored.
    MODE
    Input
    Mode. When HIGH, transmit, when LOW receive
    START
    Input
    HIGH starting input data processing
    READ
    Output
    Read request for the input data byte
    DATA_VALID
    Input
    HIGH when valid data byte present on the input
    WRITE
    Output
    Write to the output interface
    OUT_READY
    Input
    HIGH when output interface is ready to accept data byte
    D[7:0] Input Input Data
    Q[7:0] Output Output Data
    DONE Output Data processing completed
     

    Function Description

     

    The Advanced Encryption Standard (AES) algorithm is a new NIST data encryption standard as defined in the
    http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

    The WPA2 implementation fully supports the AES algorithm for 128 bit keys in Counter Mode (CTR) method of encryption with CBC message integrity check as required by the CCM protocol of the 802.11i standard.

    The core is designed for flow-through operation, with byte-wide input and output interfaces. CCM key and nonce material precedes the frame in the flow of data. WPA2 supports encrypt and decrypt modes

     
     

    Implementation Results

     

    Device Utilization and Performance

     
    Representative area/resources figures are shown below.
     
    Technology
    Area / Resources
    TSMC 0.18 u
    8900 gates
    Altera FPGA
    1362 LUT
    Xilinx FPGA
    866 slices
     

    Export Permits

     
    US Bureau of Industry and Security has assigned the export control classification number 5E002 to our AES core. The core is eligible for the license exception ENC under section 740.17(A) and (B)(1) of the export administration regulations. See the licensing basics page for links to US government sites and more details.
     

    Deliverables

     

    HDL Source Licenses

    Netlist Licenses

       
    • Synthesizable Verilog RTL source code
    • Testbench (self-checking)
    • Vectors for testbenches
    • Expected results
    • Simulation script
    • Synthesis script
    • User Documentation
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbenches
    • Expected results
    • Place & Route script
    • Simulation script
     

    Contact Information

     

    IP Cores, Inc.
    3731 Middlefield Rd.
    Palo Alto, CA 94303, USA
    Phone: +1 (650) 815-7996

    E-mail: info@ipcores.com
    www.ipcores.com
     
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