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Security, Compression, FEC, and DSP IP Cores for ASIC and FPGA Applications

IP Cores, Inc. specializes on IP cores for semiconductors, primarily in the security and cryptography area as well as few compression and DSP cores. Whatever your needs are in the areas of hardware encryption (AES/DES/SNOW3G/ZUC and other ciphers, MACsec, IPsec, SSL/TLS, IEEE 802.16e, P1619, 802.1AE),  content protection, lossless compression, LDPC/Reed-Solomon FEC, or FFT, our IP cores are usually the smallest, fastest, and lowest-cost choices on the market.
8/13/2014 IP Cores, Inc. Ships a Multichannel AES/DES Encryption IP Core Targeting the Cable Headend Designs
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Tiny encryption IP cores start at few thousand ASIC gates or few hundred FPGA slices

Ultra-compact AES IP core implements Rijndael encryption in compliance with the NIST Advanced Encryption Standard (AES, FIPS-197) with 128-bit and 256-bit keys. Base AES1 core is self-contained (no external memory, key expander included), yet very small (less than 3,000 gates). Supports ECB, CFB, CBC, OFB and CTR modes. Core is FIPS-197 certified. Datasheet.
DES / triple DES core Ultracompact DES1 implements DES and 3DES per NIST FIPS 46-3 in just 3K ASIC gates. DES1 Datasheet.
AES Key Wrap IP core AKW1 implements key wrap and unwrap per NIST specification using both 128 and 256 Key Encryption Keys (KEK). AKW1Datasheet.
Generic CCM Core CCM1 provides full flow-through implementation of the CCM (CTR+CBC) encryption and decryption for use in generic CCM applications. Datasheet.
Pseudo Random Generator PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Datasheet
True Random Generator TRNG1 core contains a true random number generator suitable for ASIC and all popular FPGA families as well cryptographically secure pseudo-random number generator per NIST publication SP800-90. Datasheet
Kasumi block cipher  KSM1 core implements encryption per ETSI SAGE specification and the 3GPP publication TS 35.202. Datasheet

SNOW 3G 3GPP LTE stream cipher
SNOW3G1 implements the keystream generation for 3GPP  LTE algorithms UEA2 and UIA2 per ETSI SAGE specification. Datasheet.
SHA  SHA cores provide implementation of cryptographic hashes SHA-1 (core SHA1), SHA-2 (cores SHA2-256 and SHA2-512). Datasheet.
Combo GCM/CCM/EAX  The GCE1-MP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard and encryption/authentication modes GCM, CCM, CCM*, and EAX’. Datasheet.
ZUC Cipher with EEA3/EIA3 Support  Implementation of the ZUC cipher used in the Chinese 3GPP mobile phoen market with support for the EIA3/EEA3 modes. Datasheet.
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Scalable high throughput IP core families deliver encryption at 10-100 Gbps data rates 

GCM (IEEE802.1ae) High-speed implementation of the AES/GCM (Galois/Counter Mode) encryption and decryption for IEEE 802.1AE (MACSec) standards. GCM1 is a compact core family starting at less than 13K ASIC gates with target throughput from 1 to 6 Gbps (scalable to 10 Gbps). GCM1 Datasheet. GCM2 is a high-performance scalable family of cores for 128-bit AES keys and target throughput between 5 and 40 Gbps (scalable to 70-100 Gbps). GCM2 Datasheet. GCM3 core family is similar to GCM2, but supports key sizes to 256 bits. GCM3 Datasheet.  GCM10 family delivers the ultimate performance of 120 Gbps and above.
XTS (IEEE P1619) A very high-throughput families of the XEX-AES cores supporting the IEEE P1619 standard. XTS2 series supports encryption and decryption with the 128-bit keys. XTS2 Datasheet. XTS3 supports both 128 and 256-bit keys. XTS3 Datasheet.
Combo XTS/GCM A combined high-speed implementation of the AES-XTS and AES-GCM modes encryption and decryption supporting IEEE P1619 and 802.1ae standards. GXM2 is a compact core for 128-bit keys. GXM2 Datasheet. GXM3 core is similar to GXM2, but allows 256-bit AES keys. GXM3Datasheet.
Combo XTS/GCM/CBC GXC3 core addresses storage and network storage applications that in addition to XTS and GCM require legacy CBC mode of the AES cipher.  GXC3Datasheet.
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Inline encryption IP cores provide cryptography for communication standards

G.hn (G.9960) CCM Core Full flow-through implementation of the CCM (CTR+CBC) encryption and decryption according to the ITU G.9960 standard.Datasheet.
WiMax 802.16e CCM Core Full flow-through implementation of the CCM (CTR+CBC) encryption and decryption according to the IEEE 802.16e standard.Datasheet.
WiFi 802.11i CCM Core Full flow-through implementation of the CCM (CTR+CBC, CCMP) encryption and decryption according to the IEEE 802.11i (WPA, WPA2) WLAN standard. The core uses less than 9,000 gates.Datasheet.
Zigbee CCM* A version of this core is also available for IEEE 802.15.4 standard (IEEE 802.15.4 is used by the ZigBee Alliance as a base of its ZigBee™ specification. Datasheet. Datasheet.
UWB MBOA CCM Core Full flow-through implementation of the CCM (CTR+CBC) encryption and decryption according to the Multi-Band OFDM (MBOA) standard. Datasheet.
Generic CCM Core CCM1 provides full flow-through implementation of the CCM (CTR+CBC) encryption and decryption for use in generic CCM applications. Datasheet.
CMAC/XCBC Core CMAC1 provides flow-through implementation of the CMAC and XCBC cryptographic hashes. Datasheet.
CCMP/TKIP/RC4 WiFi Core WPA3 provides flow-through implementation of the all WiFi chipher suites with encryption context lookup option. Datasheet.
AES-CCM/CMAC Core CCM2 provides flow-through implementation of the AES-CCM and CMAC algorithms. Datasheet.
WAPI rotocol Processor WPI1 provides flow-through implementation of the Chinese WAPI stadard using the SMS4 algorithms. Datasheet.
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IP cores for RSA and Elliptic Curve Cryptography (ECC) acceleration

RSA1-E implements the RSA exponentiation to enable low-power operation of the battery-powered devices Datasheet.
ECC1 implements the “point multiplication” and "point verification" operations, and is extremely compact at 10K gates. Datasheet.
ECC1-PM implements the most time-consuming operation of the ECC cryptography, the “point multiplication” Datasheet.
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IP cores for Compression and Encryption

LZR1 implements the lossless compression algorithm on short units of data (“frames”). The core supports frame sizes up to 4096 bytes. Datasheet.
LXP2 implements the lossless compression /decompression algorithm and AES-XTS encryption /decryption on units of data (“blocks”). Datasheet.
LZR2 is a very low-latency compression core with sustained 8 bits per clock throughput.  Datasheet.
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IP core for Forward Error Correction: Cyclic, LDPC, Reed-Solomon

FEC Codec The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40 Gbps/100 Gbps operation). Datasheet.
LDPC Codecs/Reed-Solomon codecs Please contact IP Cores, Inc. for details.
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Security Processor Cores

IPsec Processor implements the IPsec standard. Flow-through (FIFO-like) and lookaside (bus mastering) versions are available, as well as external context storage support of internal context storage with built-in key lookup.. Datasheet.
SSL/TLS Processor with AXI Bus Interfacer implements the SSL/TLS standard and operates as an AXI bus-master in the data plane.. Datasheet.
MACsec Processor implements the LAN security standard IEEE 802.1ae (MACsec) that requires the NIST standard AES cipher in the GCM mode for encryption and message authentication, as well as header parsing and formatting operations on the transmitted and received packets. . Datasheet.
MACsec Processor for MoreThanIP MAC is designed for close integration with MoreThanIP Anyspeed MAC . Datasheet.
IPsec/SSL/TLS Processor implements both SSL/TLS and IPsec acceleration.  Datasheet.
HDCP Suite provides a complete HDCP 2.0 implementation.  Datasheet.
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IP cores implement FFT and Viterbi decoder algorithms

512/1024 point FFT high-performance cores support FTT and IFFT transforms. Many more variants of the FFT cores available. Datasheet.
64 Point FFT high-performance cores support FTT and IFFT transforms. Many more variants of the FFT cores available. Datasheet.
32/64/128/256/512/1024/2048/4096 Point FFT  flexible core supports FTT and IFFT low-latency transforms for ADSL, powerline, and other communication applications. Datasheet.
FFT1-32-512 core implements 32, 64, 128, 256, and 512 point FFT and IFFT in hardware that runs at the clock frequency four times higher than the input sampling frequency Datasheet.
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LRW High-speed implementation of the LRW-AES (Liskov-Rivest-Wagner) encryption and decryption. Datasheet.
Combo GCM/ LRW Combined high-speed implementations of the LRW and GCM modes encryption and decryption.GLM1 Datasheet.
GLM2 Datasheet.
802.15.3 CCM Full flow-through implementation of the CCM (CTR+CBC) encryption and decryption according to the IEEE 802.15.3 standard.Datasheet.
RC4  High performance RC4/aRC4 implementation. .Datasheet.
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